Design Project: Logic probe

Question 1:


What factors determine where potentiometers Rpot1 and Rpot2 must be set? Why are they "trimmer" potentiometers (as indicated by the special wiper symbol) and not regular panel-mount potentiometers?
The acceptable "high" and "low" voltage levels for which ever logic family is being trouble-shot will dictate where these potentiometers must be set.

Notes:
Do not simply tell your students what these acceptable voltage levels are! Let them research datasheets for instances of logic gates within the logic family desired, and let the manufacturers' data tell them what they need to know.


Question 2:


What performance parameters are important to consider for U1 and U2, considering their use in a logic probe circuit? Hint: we may want to use this logic probe to troubleshoot CMOS as well as TTL circuits.
First and foremost, we need to consider the supply voltage ranges for all integrated circuits used in this circuit. Do not use 7400-series TTL NAND gate for U2 if you ever plan to use this logic probe on digital circuits with power supply voltages in excess of 5 volts!

Notes:
Note how the comparators sink current from the LEDs rather than source current to them. This design feature was necessary, due to the construction of the LM339. In fact, there are a lot of comparators that can only sink current and not source current due to the internal use of an open-collector output stage.


Question 3:


What purpose do resistors R1 and R2 serve, and why are they so large (1,000,000 ohms each)?
If they were not in the circuit, the logic probe would indicate a "high" condition with the probe floating. In place, the resistors force an ïndeterminate" state with a floating probe.

Notes:
A less obvious feature of these resistors is that they force the circuit under test to drive a bit of current to (or from) the probe. This is good, as it may help to show a gate with a "weak" output, such as one that is mildly overloaded. Lower values for R1 and R2 would accentuate this feature, but would also make it trickier to set the high/low threshold potentiometers (Rpot1 and Rpot2).
Another not-so-obvious design feature is that resistors R1 and R2 establish a default input voltage level that is between the two threshold settings established by the potentiometers. In my first design, I connected R1 and R2 to the power supply rails, respectively. This set the default (floating) input voltage at 1/2 V, which worked fine for CMOS logic levels but not for TTL. By having the resistors set a default input voltage between the two threshold adjustments, a floating probe is guaranteed to indicate ïndeterminate" no matter where the threshold potentiometers are set.


Question 4:


Re-design the example circuit so that a NAND logic gate is not required. Instead, think of a way you could use discrete components to do the same job.
I'll leave this part up to you!

Notes:
Not only will a discrete transistor have a wider voltage range it can operate over (compared to a logic gate), but it is a good review of transistor circuit theory and a practical example of implementing a simple logic function without the benefit of integrated circuits.


Question 5:


An extra feature you could add to the logic probe circuit is a pulse indication LED. This LED momentarily turns on whenever there is a transition from high-to-low or from low-to-high:


Actually, what the pulse indicator circuit detects is a transition to the ïndeterminate" state, which always lies between "high" and "low." A pulse indication feature is nice to have in some circumstances, since it shows the presence of pulses which may be too brief to light up either the "high" or "low" LED. The two additional NAND gates ßtretch" the pulse time so that the "pulse" LED's blink is long enough to see. The duration of the LED's blink is set by resistor R7 and capacitor C2.
Explain how the pulse indication circuitry works.
NAND gates U4 and U5 form a monostable multivibrator circuit. A low input sensed by U4 at the output of U3 (indicating an indeterminate state) forces U4 to output a high signal, which is inverted by U5 to energize the "Pulse" LED and also hold U4 in that state even when the output of U3 goes high again. This state cannot last indefinitely, though, because the RC network of R7 and C2 brings the input of U5 to a low state over time, thus "resetting" the pulse indication circuit.

Notes:
I recommend a 0.47 mF capacitor for C2 and a 100 kW resistor for R7. The added feature of a pulse indicator LED is particularly nice because it makes use of what would otherwise be unused gates in a 4011 CMOS NAND gate IC. The only added componentry is the fourth LED, current limiting resistor R6, capacitor C2, and resistor R7.


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