Building A Synchronous Clock

The quartz clocks which have dominated time-keeping for the past 20 years or so have one problem: their errors, although slight, are cumulative. After running for several months the errors can be significant. Sometimes you can correct these if you can slightly tweak the crystal frequency but otherwise you are forced to reset the clock at regular intervals. By contrast, mains-powered synchronous clocks are kept accurate by the 50Hz mains distribution system and they are very reliable, except of course, when a blackout occurs.

This circuit converts a quartz clock to synchronous mains operation, so that you can have at least one clock in your home which shows the time. First, you need to obtain a quartz clock movement and disassemble it down to the PC board. For instructions on how to do this, see the article on a "Fast Clock For Railway Modellers" in the December 1996 issue of SILICON CHIP. Then isolate the two wires to the clock coil and solder two light duty insulated hookup wires to them (eg, two strands of rainbow cable). Drill a small hole in the clock case and pass the wires through them. Then reassemble the clock case.

Circuit diagram:
Building a synchronous clock circuit schematic
A Synchronous Clock Circuit Diagram

To test the movement, touch the wires to the terminals of an AA cell, then reverse the wires and touch the cell terminals again. The clock second hand should advance on each connection. The circuit is driven by a low voltage AC plug pack. Its AC output is fed to two bridge rectifiers: BR1 provides the DC supply while BR2 provides positive-going pulses at 100Hz to IC1a, a 4093 NAND Schmitt trigger. IC1a squares up the 100Hz pulses and feeds them to the clock input of the cascaded 4017 decade counters. The output at pin 12 of IC3 is 1Hz.

This is fed to IC4, a 4013 D-type flipflop, which is connected so that its two outputs at pins 12 & 13 each go positive for one second at a time. As these pulses are too long to drive the clock movement directly, the outputs are each fed to 4093 NAND gates IC1b & IC1c where they are gated with the pin 3 signal to IC4. This results in short pulses from pins 3 & 10 of IC1 which drives the clock via limiting resistor R1. The value of R1 should be selected on test, allowing just enough current to reliably drive the clock movement.
Author: A. J. Lowe - Copyright: Silicon Chip